| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce the chip area of a test circuit of a PLL circuit. <P>SOLUTION: When testing a frequency divider PS, a test control voltage signal TC and a RF test signal TS are supplied to input terminals IN1 and IN2 through a balun T1. The test control voltage signal TC flows through resistors R1 and R2 when the NPN transistor Q0 is turned on, the operation of a voltage controlled oscillator V1 and a buffer B10 is stopped because the current from a current source I1 is not supplied, and the output impedance of the buffer B10 becomes high. Since the potentials of input terminals IN1 and IN2 have the potential of the test control voltage signal TC, the varactor diodes VD1 and VD2 are in a forward bias state and the capacitance becomes larger. The RF test signal TS is input to the frequency divider PS through the varactor diodes VD1 and VD2 without being influenced by the buffer B10 with high impedance. <P>COPYRIGHT: (C)2008,JPO&INPIT |
