| 摘要 |
PROBLEM TO BE SOLVED: To provide a technique capable of enhancing test efficiency in the semiconductor circuit. SOLUTION: The circuit under test outputs test resultant data synchronizing with clock signal CLK2 outputted from an OR circuit 12. A ring oscillator 16 oscillates ring clock signal RCLK at a predetermined frequency out of synchronization with test clock signal TCLK at the time of normal operation mode and changes ring clock signal RCLKA synchronized with test clock signal TCLK at the time of test operation mode. An OR circuit 12 uses the ring clock signal RCLKA as a clock signal CLK2 at the time of normal operation mode and uses ring clock signal RCLKA as a condition signal deciding whether to output the test clock signal TCLK as a clock signal CLK2 at the time of the test operation mode. COPYRIGHT: (C)2008,JPO&INPIT
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