| 摘要 |
<p>A method for fabricating a flash memory device is provided to reduce interference capacitance between gate patterns for a cell by forming voids between gate patterns for the cell. Gate patterns(200A,200B,200C) for a cell and gate patterns(300A,300B) for a select transistor are formed on a semiconductor substrate(101). A buffer insulation layer(108) is formed along the surface of the resultant structure, made of an oxide. An insulation layer(109) is formed in a manner that voids are formed in a space between the gate patterns for the cell, made of a material with a bad gap-fill characteristic. A nitride layer is formed on the insulation layer. A spacer(119) is formed on one lateral surface of each gate pattern for the select transistor by a spacer etch process.</p> |
