| 摘要 |
PROBLEM TO BE SOLVED: To realize a reset signal controller capable of stably starting up a CPU etc. and shortening an output period of a reset pulse signal. SOLUTION: A CPU 2 is provided with an oscillation circuit 5 to which a crystal 4 is connected, and the oscillation circuit 5 is provided with a PLL circuit 6 for generating a clock signal 7. The clock signal of the PLL circuit 6 is supplied as a feedback signal 8 to the reset signal control circuit 1. The reset control circuit 1 outputs a reset command signal 3 to the CPU 2, and monitors the feedback signal 8. The reset command 3 is completed when the time required for stable state of the clock signal 7 and a minimum time Tfix required for stabilization of the CPU 2 elapse. Thus, unlike a conventional technique, a reset command is not required to continue until a set stabilization time Tosc elapses and the CPU 2 starts its operation earlier. COPYRIGHT: (C)2008,JPO&INPIT
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