发明名称 |
Method system and apparatus for floorplanning programmable logic designs |
摘要 |
A method ( 600 ) of designing a programmable logic device can include the steps of identifying a cost function that penalizes floorplans of a circuit design that do not fit on the programmable logic device ( 605 ) and defining modules having components of a same type ( 615 ). A set of shapes associated with a module can be determined ( 610 ). The circuit design can be annealed ( 620 ) to determine a floorplan using the cost function and the set of shapes for the module.
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申请公布号 |
US7313778(B1) |
申请公布日期 |
2007.12.25 |
申请号 |
US20040787326 |
申请日期 |
2004.02.26 |
申请人 |
XILINX, INC. |
发明人 |
STENZ GUENTER;DASASATHYAN SRINIVASAN;AGGARWAL RAJAT;SAUNDERS JAMES L. |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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