发明名称 |
Annealed wafer and method for manufacturing the same |
摘要 |
The present invention provides an annealed wafer which has a wafer surface layer serving as a device fabricating region and having an excellent oxide film dielectric breakdown characteristic, and a wafer bulk layer in which oxide precipitates are present at a high density at the stage before the wafer is loaded into the device fabrication processes to give an excellent IG capability, and a method for manufacturing the annealed wafer. The present invention is directed to an annealed wafer obtained by performing heat treatment on a silicon wafer manufactured from a silicon single crystal grown by the Czochralski method, wherein a good chip yield of an oxide film dielectric breakdown characteristic in a region having at least a depth of up to 5 mum from a wafer surface is 95% or more, and a density of oxide precipitates detectable in the wafer bulk and each having a size not smaller than a size showing a gettering capability is not less than 1x10<SUP>9</SUP>/cm<SUP>3</SUP>.
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申请公布号 |
US7311888(B2) |
申请公布日期 |
2007.12.25 |
申请号 |
US20050530557 |
申请日期 |
2005.04.07 |
申请人 |
SHIN-ETSU HANDOTAI CO., LTD. |
发明人 |
TAKENO HIROSHI;SAKURADA MASAHIRO;KOBAYASHI TAKESHI |
分类号 |
C30B15/20;C30B29/06;C30B33/00;C30B33/02;H01L21/322 |
主分类号 |
C30B15/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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