| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce power consumption by preventing the deterioration of processing performance due to dynamic clock control in a semiconductor integrated circuit. <P>SOLUTION: A main circuit 10 performs access to a subordinate circuit 70 by using a subordinate circuit control signal 11, and a clock gating control circuit 20 senses access from the main circuit 10 to the subordinate circuit 70, and generates a gating control signal 40 as a signal for controlling the ON/OFF of a clock 50 to be generated by a clock generation circuit 60, and to be supplied to the subordinate circuit 70. Furthermore, a clock gating validity control circuit 30 generates a gating permission signal 41 for controlling the validity/invalidity of the gating control signal 40, and the gating control signal 40 validated by the gating permission signal 41 controls the ON/OFF of the clock 50 from the clock generation circuit 60, and controls clock supply to the subordinate circuit 70. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
