| 摘要 |
For methods of creating pluralities of semiconductor test structure layouts from a graphical specification, systems include a GUI to draw objects representing shapes of such layout, and to parameterize those objects to size and interrelate those objects. The GUI supports placement of cells in hierarchical layers. The graphical specification is parsed into an ASCII descriptor file from which node information is extracted and connection information among nodes preserved in separate graphs for an X direction and a Y direction of the layout. That node and connection information is further processed to obtain equations having variables (parameters) that relate points in the layout a defined point, and those equations used in forming source code that can be executed with values for the variables in the source code.
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