| 摘要 |
A semiconductor device having a stress enhanced MOS transistor and a method for manufacturing the semiconductor device are provided to prevent an etching damage to a metal silicide film, which is included in a source/drain region, and a gate pattern by using a first passivation pattern. A MOS transistor, which includes a pair of source/drain regions(74,78), gate patterns(63,66), and a sidewall spacer, is formed on a predetermined region on a semiconductor substrate(51). The gate pattern is formed on a channel region between the source/drain regions. The sidewall spacer covers a sidewall of the gate pattern. A first passivation pattern covers the source/drain regions, exposes the sidewall spacer, and covers an upper portion of the gate pattern. A thin spacer(69s) is formed by etching the exposed sidewall spacer by using the first passivation pattern as an etch mask. A stress liner is formed to cover the MOS transistor, which includes the thin spacer.
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