| 摘要 |
A memory device having a bit line equalizing unit in a cell array and a method for arranging the bit line equalizing unit in the cell array are provided to perform a rapid bit line voltage equalization by achieving bit line pair voltage equalization in the cell array part. A cell array part(301) has a bit line equalizer part equalizing a voltage of a bit line pair according to the enabling of a voltage equalizing signal. The voltage equalizing signal is a voltage equalizing signal of a bit line sense amplifier part(302) adjacent to the bit line equalizer part. The bit line equalizing part is located on the end of the bit line pair of the cell array part, and includes more than one transistor connecting the bit line pair.
|
