| 摘要 |
<P>PROBLEM TO BE SOLVED: To enhance stability by shortening the settling time of clock conversion. <P>SOLUTION: A phase comparator 10 performs phase comparison by comparing a reference clock counter value obtained by counting a reference clock with a reproduction clock step value addition result obtained by adding a supplied reproduction clock step value and latching at the timing of reproduction clock thus detecting a phase error. A loop filter 11 smoothes the detected phase error, and outputs a voltage value corresponding to the phase error. A voltage controlled oscillator 12 generates the reproduction clock by a voltage value outputted from the loop filter 11. <P>COPYRIGHT: (C)2008,JPO&INPIT |
