发明名称 |
CMOS circuit including double-insulated-gate field-effect transistors |
摘要 |
It is an object of the present invention to provide a CMOS circuit implemented using four-terminal double-insulated-gate field-effect transistors, in which the problems described above can be overcome. Another object of the present invention is to reduce power consumption in a circuit unit that is in an idle state or ready state, i.e., to reduce static power consumption. The two gate electrodes of a P-type four-terminal double-insulated-gate field-effect transistor are electrically connected to each other and are electrically connected to one of the gate electrodes of an N-type four-terminal double-insulated-gate field-effect transistor, whereby an input terminal of a CMOS circuit is formed, and a threshold voltage of the N-type four-terminal double-insulated-gate field-effect transistor is controlled by controlling a potential of the other gate of the N-type four-terminal double-insulated-gate field-effect transistor.
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申请公布号 |
US7282959(B2) |
申请公布日期 |
2007.10.16 |
申请号 |
US20050072401 |
申请日期 |
2005.03.07 |
申请人 |
NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCEAND TECHNOLOGY |
发明人 |
SEKIGAWA TOSHIHIRO;KOIKE HANPEI;LIU YONGXUN;MASAHARA MEISHOKU |
分类号 |
G11C11/41;H03K19/094;G11C11/412;H01L21/8238;H01L21/8244;H01L27/092;H01L27/11;H01L29/76;H03K19/0948 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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