发明名称 TEST FACILITATION DESIGNING APPARATUS AND TEST FACILITATION DESIGNING METHOD
摘要 <p>A test facilitation designing apparatus and a test facilitation designing method wherein multiple input/multiple output modules are also classified in type to further advance the test facilitation design. An integrated-circuit test facilitation designing apparatus (1), which facilitates the tests of data paths in an RTL circuit, comprises a pre-processing part (31) that classifies multiple input/multiple output circuit elements, which are part of the circuit elements constituting the data paths, according to a plurality of types as distinguished in a predetermined through classification for the output terminals; and a control path generating part (35) that decides, based on the type of the output terminal as classified in type, a path from an external input to an input terminal of a designated circuit element to be tested or a path from an output terminal of a designated circuit element to be tested to an external output.</p>
申请公布号 WO2007110939(A1) 申请公布日期 2007.10.04
申请号 WO2006JP306416 申请日期 2006.03.29
申请人 DATE, HIROSHI;SYSTEM JD CO., LTD. 发明人 DATE, HIROSHI
分类号 G06F17/50 主分类号 G06F17/50
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