| 发明名称 |
Buffer/voltage-mirror arrangements for sensitive node voltage connections |
| 摘要 |
The present invention is directed to buffer/voltage mirror arrangement for sensitive node voltage connections.
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| 申请公布号 |
US7276940(B2) |
申请公布日期 |
2007.10.02 |
| 申请号 |
US20040984584 |
申请日期 |
2004.11.09 |
| 申请人 |
INTEL CORPORATION |
发明人 |
SONG HONGJIANG |
| 分类号 |
H03B1/00;H03F3/347;H03F3/72;H03K19/0185;H03K19/094 |
主分类号 |
H03B1/00 |
| 代理机构 |
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代理人 |
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| 主权项 |
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