| 摘要 |
A calculation circuit for calculating a sampling phase error is provided. According to one aspect, a calculation circuit includes a first delay element chain having serially connected delay elements, for delaying a digital estimate of a decision device; a second delay element chain having serially connected delay elements, for delaying an equalized signal; a multiplier array which multiplies the undelayed digital estimate and the delayed estimates of all the delay elements of the first delay element chain by the equalized signal and the delayed output signals of all the delay elements of the second delay element chain to generate product signals; a weighting circuit multiplies the product signals generated by the multiplier array by adjustable weighting factors; and having an adder which adds the product signals weighted by the weighting circuit to the sampling phase error signal.
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