发明名称 Enhanced PFET using shear stress
摘要 A semiconductor device structure includes a gate structure disposed on a portion of substrate, source and drain regions disposed adjacent to the portion so as to form a channel region in the portion, and trench isolation regions located immediately adjacent to the source and drain regions. At least portions of the trench isolation regions include stress materials such that the materials generate shear stresses in the channel region.
申请公布号 US7274084(B2) 申请公布日期 2007.09.25
申请号 US20050905589 申请日期 2005.01.12
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 CHIDAMBARRAO DURESETI
分类号 H01L29/00 主分类号 H01L29/00
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