| 摘要 |
In an A/D conversion device, each delay unit in a pulse delay circuit has inverters INV of mxn stages (m, n are positive integers), a clock generator has m-delay lines, and each delay line has inverters INV of ixn stages (i=1, 2, . . . , and m). Those delay lines DL 1 to DLm output sampling clocks CK 1 to CKm. Each of those inverters INV has a same characteristic. In the A/D conversion device, the delay time in each of the delay lines DL 1 to DLm is adjusted by the number of the inverters INV. It is thereby possible to provide the m-sampling clocks CK 1 to CKm of a different phase DeltaT with one another, namely whose phases are preciously shifted by DeltaT with one another.
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