摘要 |
The synchronous logic device with reduced pin count scan chain includes: more than two flip/flops (SDC0, SDC1, SDC2) coupled to form a shift register for receiving a scan data input signal (ScanDataIn); a combinational logic circuit (20) for receiving device inputs, generating flip/flop inputs for the more than two flip/flops, and generating an output signal; a first multiplexer (MUX10) for providing a clock signal to the more than two flip/flops during a test mode; a second multiplexer (MUX12) for selecting between a test mode output from the shift register and the output signal from the combinational logic circuit (20), and for providing a scan data output signal (ScanDataOut). In one embodiment, the scan data input signal and the scan data output signal share an input/output pin. |
申请人 |
TEXAS INSTRUMENTS INCORPORATED;DOORENBOS, JERRY, L.;TRIFONOV, DIMITAR;GARDNER, MARCO, A. |
发明人 |
DOORENBOS, JERRY, L.;TRIFONOV, DIMITAR;GARDNER, MARCO, A. |