| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a PLL device compatible with received packet missing for establishing system synchronization according to the occurrence of packet missing. <P>SOLUTION: An oscillator 12 generates a clock signal 14 and a packet counter 16 counts an arrival period of system timing information. A packet counter 30 counts generated timing signals 18 by the arrival period, a delay amount buffer 34 latches counts by the system timing information items by two times, a subtraction circuit 40 obtains a comparison value from a difference between the two counts, an overflow correction circuit 44 corrects the count when the comparison value is greater or smaller to a degree of exceeding an error caused in the system synchronization, and further a phase difference detection circuit 48 corrects a cumulative deviation of clock positions, and an integration circuit 52 executes integration operations only when the system timing information 36 is input. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
