| 摘要 |
An integrated circuit, wafer, and method for manufacturing an integrated circuit that inhibits the analysis of the circuit via reverse engineering. An integrated circuit includes a target circuit and a reverse engineering prevention circuit. The reverse engineering prevention circuit includes a decryption circuit, a nonvolatile memory, and an automatic read/enable signal generation circuit. When provided with a decoding enable signal and decoding data, the decryption circuit decodes data to perform authentication. When the authentication is successful, the decryption circuit outputs a memory enable signal. When provided with the memory enable signal, the nonvolatile memory enables the writing of data. The automatic read/enable signal generation circuit acquires the data written to the nonvolatile memory to generate a circuit enable signal, which is provided to the target circuit to activate the target circuit.
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