发明名称 Phase lock loop and method for coded waveforms
摘要 A novel system and method is disclosed for maintaining synchronization in a communication system in which a communication signal comprising a carrier and a data signal is sent from a transmitter to a receiver which includes a phase lock loop. The receiver compares the output of a Viterbi decoder with the output of a quick decision circuit. The Viterbi decoder, which incorporates traceback, determines the minimum aggregate Euclidean distance for multiple symbols. The quick decision circuit determines the minimum Euclidean distance for a single symbol without decoding the symbol. A delay circuit is placed in series with the quick decision circuit to compensate for the traceback delay in the Viterbi decoder. If the difference in the output signals of the Viterbi decoder and the quick decision circuit is greater than a predetermined threshold, the phase error signal in the phase lock loop is prevented from updating the phase lock loop filter. A synchronization loss detector may also be used to prevent the phase error signal from updating the phase lock loop filter if synchronization loss is detected. Additionally, the output signal from the Viterbi decoder is used to extract the carrier from the received communication signal by use of a lookup table to generate phase angle information as a function of the Viterbi decoder output signal. The phase angle information is combined with the Viterbi decoder output signal to reconstitute the data signal in the communication signal. The reconstituted data signal is combined with the communication signal, which has been delayed to compensate for the traceback delay in the Viterbi decoder, in order to extract the carrier.
申请公布号 US2007195913(A1) 申请公布日期 2007.08.23
申请号 US20070651566 申请日期 2007.01.10
申请人 HARRIS CORPORATION 发明人 HESSEL CLIFFORD;VOGLEWEDE PAUL E.
分类号 H03D1/00;H03D3/24;H04L27/00 主分类号 H03D1/00
代理机构 代理人
主权项
地址