发明名称 |
Vector processing apparatus, information processing apparatus, and vector processing method for reducing simultaneous switching noise |
摘要 |
<p>A vector processing apparatus includes a plurality of vector pipeline computing units and an instruction control unit. The vector pipeline computing units operate in accordance with operation control information for instructing start and execution of processing. The instruction control unit generates operation control information and outputs the operation control information to the respective vector pipeline computing units at different timings. Since the processing operations of the vector pipeline computing units are temporarily shifted from each other, the amount of switching for the start of simultaneous operations of circuits at the start of the execution of a vector computation instruction can be reduced. As a consequence, noise caused by simultaneous switching can be reduced. An information processing apparatus and vector processing method are also disclosed.</p> |
申请公布号 |
EP1624380(B1) |
申请公布日期 |
2007.08.22 |
申请号 |
EP20050015681 |
申请日期 |
2005.07.19 |
申请人 |
NEC CORPORATION |
发明人 |
TODA, HIDEMASA |
分类号 |
G06F15/78;G06F9/38;G06F17/16;H03K17/16;H03K19/003 |
主分类号 |
G06F15/78 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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