发明名称 TERNARY LOGIC FUNCTION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a ternary logic function circuit whereby types of basic circuits for achieving all two variable ternary logic function circuits of 3<SP>3^2</SP>=19683 types can remarkably be reduced, the asymmetry of switching times can considerably be decreased, the operating speed of the logic function circuits is improved, and the symmetry of the waveform can be enhanced. SOLUTION: In the ternary logic function circuit, one-variable ternary logic function circuits C1, D1, C3, D3 conduct or interrupt three transfer gates T1, T2, T3 in response to three logical values -1, 0, 1 configuring a first input (a) to select outputs of three one-variable ternary logic function circuits B1, B2, B3 connected to a second input (b). The transfer gate T2 is configured by connecting a switch pair comprising series connection of two n-type MOS transistors in parallel with a switch pair comprising series connection of two p-type MOS transistors. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007208512(A) 申请公布日期 2007.08.16
申请号 JP20060023474 申请日期 2006.01.31
申请人 JAPAN ADVANCED INSTITUTE OF SCIENCE & TECHNOLOGY HOKURIKU 发明人 HIBINO YASUSHI;SHIRASE MASAAKI
分类号 H03K19/20 主分类号 H03K19/20
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