发明名称 DECODE CIRCUIT
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a decode circuit to which memory access is reduced in the decode circuit having output for display and output for recording and in which the output for display has a function capable of switching and outputting a decoded image and a captured image and a function by which two decoding operations are simultaneously allowed regarding the decode circuit of image information. <P>SOLUTION: Regarding the decode circuit of the image information, in the decode circuit having the output for display and the output for recording and in which the output for display has the function capable of switching and outputting the decoded image and the capture image and the function by which the two decoding operations are simultaneously allowed, the memory access is reduced by outputting normally decoded images, respectively when both of the output for display and the output for recording output are considered as the decoded images and using a simply decoded image for the recoding output when the output for display is considered as the captured image and the recording output is considered as the decoded image. <P>COPYRIGHT: (C)2007,JPO&INPIT</p>
申请公布号 JP2007208700(A) 申请公布日期 2007.08.16
申请号 JP20060025786 申请日期 2006.02.02
申请人 TOSHIBA CORP 发明人 FUKUSHIMA MICHIHIRO
分类号 H04N5/44;H04N5/92;H04N5/937;H04N7/173;H04N7/26;H04N19/00;H04N19/423;H04N19/44;H04N19/70;H04N21/426 主分类号 H04N5/44
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