| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an analog-to-digital converter (ADC) which reduces the delay amount of a middle node which receives maximum delay from the driving source of a differential resistance ladder. <P>SOLUTION: A differential analog-to-digital converter (ADC) comprises first and second resistance ladder legs, first and second amplifiers, and a plurality of comparators. Each resistance ladder leg includes two resistances having first ends that communicate with a middle node and second ends that communicate with a current source. The first amplifier applies a voltage based upon a first phase of an input signal to the middle node of the first resistance ladder leg. The second amplifier applies a voltage based upon a second phase of the input signal to the middle node of the second resistance ladder leg. The plurality of comparators each has first and second inputs, wherein the first input communicates with one of the two resistances of the first resistance ladder leg, and the second input communicates with one of the two resistances of the second resistance ladder leg. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
