发明名称 |
Semiconductor device having SOI structure including a load resistor of an sram memory cell |
摘要 |
It is an object to provide a semiconductor device having an SOI structure in which an electric potential of a body region in an element formation region isolated by a partial isolation region can be fixed with a high stability. A MOS transistor comprising a source region ( 51 ), a drain region ( 61 ) and an H gate electrode ( 71 ) is formed in an element formation region isolated by a partial oxide film ( 31 ). The H gate electrode ( 71 ) electrically isolates a body region ( 13 ) formed in a gate width W direction adjacently to the source region ( 51 ) and the drain region ( 61 ) from the drain region ( 61 ) and the source region ( 51 ) through "I" in a transverse direction (a vertical direction in the drawing), a central "-" functions as a gate electrode of an original MOS transistor.
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申请公布号 |
US7256463(B2) |
申请公布日期 |
2007.08.14 |
申请号 |
US20040841469 |
申请日期 |
2004.05.10 |
申请人 |
RENESAS TECHNOLOGY CORP. |
发明人 |
MATSUMOTO TAKUJI;MAEDA SHIGENOBU;IWAMATSU TOSHIAKI;IPPOSHI TAKASHI |
分类号 |
H01L27/04;H01L27/11;H01L21/336;H01L21/762;H01L21/822;H01L21/8238;H01L21/8244;H01L21/84;H01L27/08;H01L27/092;H01L27/10;H01L27/12;H01L29/786 |
主分类号 |
H01L27/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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