发明名称 Phase comparator, clock data recovery circuit and transceiver circuit
摘要 A phase comparator comprises a latch unit for latching the input data signal in parallel on rising/falling edges of the respective clock signals respectively, an error signal output unit for outputting m error signals respectively indicative of differences in phase between the transient edge of the input data signal and the transient edges of the respective clock signals and each having a minimum pulse width of (m/2-1)xT or more, based on respective output signals produced from the latch unit and the respective clock signals, an input unit for inputting the respective output signals produced from the latch unit in parallel on the rising/falling edges of the respective clock signals and a reference signal output unit for outputting m reference signals whose pulse widths are (m/2)xT, based on output signals produced from the input unit and the respective clock signals.
申请公布号 US7257184(B2) 申请公布日期 2007.08.14
申请号 US20030391298 申请日期 2003.03.19
申请人 NTT ELECTRONICS CORPORATION 发明人 OTOMO YUSUKE
分类号 H03D3/24;H03D13/00;H03L7/089;H03L7/091;H03L7/099;H04J3/04;H04L7/033 主分类号 H03D3/24
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