DATA OUTPUT APPARATUS OF SEMICONDUCTOR MEMORY

摘要

A data output apparatus of a semiconductor memory is provided to improve timing margin by aligning global data and a pipe latch driving signal to a rising edge of an input/output enable signal. A first delay unit(210) outputs an input/output sense amplifier strobe signal by delaying an input/output enable signal. A pipe latch strobe signal generation unit(240) receives the input/output enable signal and the input/output sense amplifier strobe signal. A second delay unit(220) receives a pipe latch strobe signal output from the pipe latch strobe signal generation unit. A pipe latch unit(260) receives global data from a global data line in response to a pipe latch driving signal output from the second delay unit.