| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an integrated circuit processable without malfunction, even if an asynchronous reset is inputted directly. <P>SOLUTION: This integrated circuit device 10 includes a CPU 10 constituted by including a flip-flop 20 wherein an asynchronous reset input 90 is connected to an asynchronous input, and a light disable signal generation circuit 50 for generating a light disable signal 52 changing from a disable state to an enable state by the first clock after asynchronous reset input cancellation based on the asynchronous reset input 90 and a clock input 80. The CPU 10 includes a write prevention circuit 60 for preventing new data from being written into the flip-flop 20 while the light disable signal 52 is in the disable state. Also a light disable signal changing from the disable state to the enable state by delaying the asynchronous reset input cancellation for a prescribed clock may be generated. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
