| 摘要 |
A memory device including an array of resistive memory cells, which are arranged in columns and rows, and wherein each resistive memory cell each is connected to a word line, to a bit line, and to a reference electrode. The word lines are assigned to the rows and the bit lines are assigned to the columns. The resistive state of the resistive memory cells corresponds to a logical state thereof, and the memory device further comprises an evaluation device, which is coupled to the bit lines, for evaluating the resistive state of at least one of the resistive memory cells during a reading operation. The respective resistive memory cell is selected by addressing the word line to which the resistive memory cell is connected.
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