| 摘要 |
A circuit for entering a test mode in a semiconductor memory device is provided to improve time efficiency by outputting a plurality of test signals simultaneously by preventing the loss of a test mode code in entering the test mode. A test mode decoder(400) generates a plurality of decoding signals by decoding a test mode code. A latch unit(500) generates and stores a plurality of latch signals by latching the decoding signals in correspondence to the input of a reset signal. A test signal output unit(600) outputs a plurality of test signals defining the latch signals stored in the latch unit as a test mode in correspondence to the input of a test mode operation signal indicating a test mode operation.
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