发明名称 Flow control mechanism in a data processing pipeline
摘要 Herein described are at least a system and a method for regulating data flow in a data pipeline that may be used in a video processing system. The system comprises a processor, one or more data buffers, and one or more processing stations. The one or more data buffers may be used to buffer corresponding processing stations. Each of the one or more processing stations may comprise a switching circuitry that is used to inhibit data transmission when a hold signal is received from the processor. The processor may send the signal in response to a feedback control signal generated by the one or more processing stations. The method may comprise determining if the processing time of a processing station exceeds a specified time. The method further comprises generating a feedback control signal to a processor if the specified time is exceeded.
申请公布号 US2007177581(A1) 申请公布日期 2007.08.02
申请号 US20060344329 申请日期 2006.01.31
申请人 RODGERS STEVE W;MAMIDWAR RAJESH 发明人 RODGERS STEVE W.;MAMIDWAR RAJESH
分类号 H04L12/66 主分类号 H04L12/66
代理机构 代理人
主权项
地址