| 摘要 |
A two phase, second order capacitance-to-digital (CD) modulator includes a first stage sigma-delta integrator that forms charge packets as a function of sensor capacitance during an auto-zero phase and integrates the packets during an integration phase to produce an output voltage. The first stage integrator holds its output voltage during the auto-zero phase, so that a second stage sigma-delta integrator can sample the first stage output voltage during the auto-zero phase and integrate the sampled voltage during the integration phase.
|
