发明名称 |
Methods and semiconductor structures for latch-up suppression using a conductive region |
摘要 |
Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate between the first and second doped wells. The trench is partially filled with a conductor material that is electrically coupled with the first and second doped wells. Highly-doped conductive regions may be provided in the semiconductor material bordering the trench at a location adjacent to the conductive material in the trench.
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申请公布号 |
US2007170543(A1) |
申请公布日期 |
2007.07.26 |
申请号 |
US20060340752 |
申请日期 |
2006.01.26 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
FURUKAWA TOSHIHARU;HORAK DAVID V.;KOBURGER CHARLES W.III;MANDELMAN JACK A.;TONTI WILLIAM R. |
分类号 |
H01L29/00 |
主分类号 |
H01L29/00 |
代理机构 |
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代理人 |
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地址 |
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