发明名称 |
FUSI integration method using SOG as a sacrificial planarization layer |
摘要 |
A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90 . The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.
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申请公布号 |
US2007173047(A1) |
申请公布日期 |
2007.07.26 |
申请号 |
US20060338028 |
申请日期 |
2006.01.24 |
申请人 |
LU JIONG-PING;OBENG YAW S;JIANG PING;TRAN JOE G |
发明人 |
LU JIONG-PING;OBENG YAW S.;JIANG PING;TRAN JOE G. |
分类号 |
H01L21/4763;H01L21/3205 |
主分类号 |
H01L21/4763 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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