A display panel is provided to minimize parasitic capacitance between a gate line and a pixel electrode by forming a low-dielectric-constant organic layer between the gate line and the pixel electrode. Gate line(129) is formed on a first substrate, and includes an expansion part. Data lines(171,179) intersect the gate lines. A thin film transistor is connected to the data line and the gate line. A first protective layer covers the thin film transistor. A second protective layer overlaps the expansion part of the gate line and is formed of an organic material. A pixel electrode(191) is formed on the first and second protective layers, and is connected to the thin film transistor. The second protective layer is partially formed on the expansion part of the gate line.
申请公布号
KR20070076956(A)
申请公布日期
2007.07.25
申请号
KR20060006520
申请日期
2006.01.20
申请人
SAMSUNG ELECTRONICS CO., LTD.
发明人
KIM, BEOM JUN;KWON, YEONG KEUN;KIM, SUNG MAN;HAN, HYE RHEE;LEE, JONG HYUK;KIM, YU JIN