STRUCTURE TO MONITOR ARCING IN THE PROCESSING STEPS OF METAL LAYER BUILD ON SILICON-ON-INSULATOR SEMICONDUCTORS

摘要

The present invention addresses detection of charge-induced defects through test structures that can be easily incorporated on a wafer to detect charge-induced damage in the back-end-of-line processing of a semiconductor processing line. A test macro is designed to induce an arc from a charge accumulating antenna structure to another charge accumulating antenna structure across parallel plate electrodes. When an arc of a predetermined sufficient strength is present, the macro will experience a voltage breakdown that is measurable as a short. The parallel plate electrodes may both be at the floating potential of the microchip to monitor CMP-induced or lithographic-induced charge failure mechanisms, or have one electrode electrically connected to a ground potential structure to capture charge induced damage, hence having the capability to differentiate between the two.