| 摘要 |
<p>A layout for improving a gate process margin and a method for forming a gate pattern using the same are provided to reduce an etch bias on a gate pattern by decreasing the distance between gate patterns on active regions using concave and convex portions of the active regions. A layout for improving a gate process margin includes two active regions and two gate patterns. The two active regions(100) are spaced apart from each other on a semiconductor substrate. Opposite sides of the two active regions have a concave portion(105) and a convex portion(106), respectively. The two gate patterns(200) are set within the two active regions, respectively. The gate pattern is formed like a line type structure. The distance between the two gate patterns is reduced due to the concave and convex portions of the active regions, so that an etch bias on the gate pattern is reduced.</p> |
