| 摘要 |
An architecture capable of Content Based Adaptive Binary Arithmetic Coding (CABAC) decoding at the syntax element level is disclosed. The architecture employs a multi-stage stage pipeline to implement the functions of CABAC bit parsing and decoding processes based on the H.264 CABAC algorithm. Each stage can be carried out in one clock cycle, and not all stages are executed for every bit (e.g., average of 4 cycle per bit, or 30 frames per second). The architecture can be implemented, for example, using gate-level logic state machines as part of a system-on-chip (SOC) solution for a video/audio decoder for use in high definition television broadcasting (HDTV) applications. Other such video/audio decoder applications are enabled as well. |
