发明名称 ENCRYPTION PROCESSING APPARATUS
摘要 PROBLEM TO BE SOLVED: To provide an encryption processing apparatus with high immunity to a DFA attack. SOLUTION: As clock signals for controlling data storage timing to registers for storing a result of round arithmetic operations, separate clocks (CLK1, CLK2) are respectively given to a master and a slave for configuring each register, and an output of, e.g. an oscillator applies retiming to the clocks to produce sets of a plurality of clock signals (CLK-1, CLK1-2) to (CLK2-n, CLK-2-n) with a plurality of timings, which are selectively supplied to the master and the slave as register configuration circuits thereby achieving bit data capture in the different timings. Through the configuration above, the encryption processing apparatus with high immunity to a DPA attack by statistic processing of a consumed current is obtained. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007174025(A) 申请公布日期 2007.07.05
申请号 JP20050365871 申请日期 2005.12.20
申请人 SONY CORP 发明人 NOBUKATA HIROMI
分类号 H04L9/10 主分类号 H04L9/10
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