| 摘要 |
Disclosed is a method of manufacturing a CMOS image sensor. The method reduces a difference in the height of the interconnection layers over the logic area and pixel array area. At the same time, the method also provides a closer proximity between the micro-lenses and the pixel array. A semiconductor substrate has a pixel array area and a logic circuit area. A lower interconnection is formed over the semiconductor substrate. An interlayer dielectric layer is formed over the lower interconnection. A via hole is formed by removing a portion of the interlayer dielectric layer in the logic circuit area. An upper interconnection is formed by filling the first via hole with a metal, then planarizing the surface.
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