发明名称 Process of automatically translating an extended activity diagram into a hardware component graph
摘要 A process of automatically translating an extended activity diagram (EAD) into a hardware component graph (HCG). For translating the high level programming language into a Very High Speed Integrated Circuit Hardware Description Language (VHDL), the high level programming language is first translated into an activity diagram (AD), then the AD is translated into an HCG, which can indicate a connection relation between hardware components, and finally corresponding HDL codes are generated according to the HCG
申请公布号 US2007157187(A1) 申请公布日期 2007.07.05
申请号 US20060471483 申请日期 2006.06.21
申请人 TATUNG COMPANY 发明人 CHENG FU-CHIUNG;YU SHIN-HWAY;CHEN KUAN-YU;CHEN JIAN-YI;CHIANG MING-SHIOU;CHANG SHU-MING;WU HUNG-CHI;WANG PING-YUN
分类号 G06F9/45;G06F9/44 主分类号 G06F9/45
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