| 摘要 |
In high current integrated circuit wafer test applications, a high capacitance density capacitor may be formed in association with a probe card at a position closer to a wafer under test. This reduces the power path impedance, improving transient power delivery of a probe card. That is because now the capacitance is positioned more closely to the wafer under test, reducing path impedance. The capacitance density may be at higher, improving transient power delivery.
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