| 摘要 |
A gate array is provided to use an unused gate interconnection of a unit cell instead of a metal interconnection by installing a contact in a gate terminal part of an unused transistor in the unit cell to be connected to the metal interconnection. A plurality of unit cells are disposed in parallel on a semiconductor substrate, having the same pattern including first and second MOS transistors. The first and second MOS transistors have gates, sources and drains, respectively. The gates of the first and second MOS transistors are interconnected by a gate interconnection having first and second gate terminal parts. A plurality of metal interconnections are formed on the unit cell by interposing an insulation layer. The metal interconnection, the first gate terminal part, the second gate terminal part, and the source/drain are electrically connected by a plurality of contacts(31). In the unit cell in which the first or second MOS transistor is not used as a transistor, the first and second gate terminal parts have the contacts. The unit cell can have a power potential region and a ground potential region. The source and drain of the first MOS transistor not used as the transistor and the source and drain of the second MOS transistor not used as the transistor are connected to the power potential region and the ground potential region.
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