发明名称 Alternating clock signal generation for delay loops
摘要 A delay loop (e.g., a voltage-controlled delay loop) has (at least) two devices (e.g., interpolators) for generating clock signals for injection into the delay elements of the delay loop in a leap-frog manner, in which, while one interpolator is generating the clock signal currently selected for injection, the other interpolator can be controlled to generate the next clock signal to be selected for injection. This leap-frog technique can provide more settling time for generating injected clock signals than implementations that rely on a single interpolator.
申请公布号 US7236037(B2) 申请公布日期 2007.06.26
申请号 US20050138777 申请日期 2005.05.26
申请人 AGERE SYSTEMS INC. 发明人 ABEL CHRISTOPHER J.;SINDALOVSKY VLADIMIR;ZIEMER CRAIG B.
分类号 H03K3/00 主分类号 H03K3/00
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