| 摘要 |
<P>PROBLEM TO BE SOLVED: To attain high speed read-out even with small signal amplitude. <P>SOLUTION: A memory cell 1 has: a first amplifier transistor AT1 and a first read transistor RT1 which are cascade-connected between a second bit line BL_ and a voltage supply line CSL; a second amplifier transistor AT2 and a second read transistor RT2 which are cascade-connected between a first bit line BL and the voltage supply line CSL; a first write transistor WT1 connected between the control node of the first amplifier transistor AT1 and the first bit line BL; and a second write transistor WT2 connected between the control node of the second amplifier transistor AT2 and the second bit line BL_. Each control node of the first and the second read transistors RT1, 2 is connected to a read word line RWL, and each control node of the first and the second write transistors WT1, 2 is connected to a write word line WWL. <P>COPYRIGHT: (C)2007,JPO&INPIT |
