Compensation circuit for sigma-delta-analog-digital-converter, has modeling circuit producing modeled error signal, where modeled jitter error signal is subtracted from output signal for producing compensated digital output signal

摘要

The circuit (1) has a clocked digital/analog converter for compensation of jitter error caused by a jitter of a clock signal. A detection circuit (1A) detects the jitter and a modeling circuit produces a modeled error signal that reproduces the error. The modeled jitter error signal is subtracted from a digital output signal of a sigma-delta-analog-digital-converter for producing a compensated digital output signal. An independent claim is also included for a method for clock jitter compensation in a sigma-delta-analog-digital-converter.