| 摘要 |
A bus processing apparatus including a first buffer, a second buffer, an input control unit, an output control unit and a synchronous control unit is provided. The input control unit generates a storing address for deciding to output the transmitter data to either the first buffer or the second buffer according to a first timing and a data enable signal. The synchronous control unit receives and compares the storing address with a reading address in accordance with a second timing in order to output a data ready signal. The output control unit generates the reading address according to the second timing and the data ready signal, and reads the data stored in the first buffer or in the second buffer according to the reading address to output a receiver data to the receiver. Wherein, the frequency of second timing is not lower than the frequency of first timing.
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