| 摘要 |
A method for generating an integrated circuit (IC) is provided wherein signal delays are transferable across two synthesis libraries where each library is associated with a different IC fabrication process. The method initiates with describing an IC design through a hardware description language (HDL). The method includes identifying logic signal delay points within the HDL. Then, technology-independent logic signal delay code is inserted within the delay points of the HDL representation. A system for designing an IC is also provided.
|
