发明名称 System and method for encoding packet header to enable higher bandwidth efficiency across PCIe links
摘要 A computer system that employs Peripheral Component Interconnect Express (PCIe) links includes devices that generate a PCIe packet having a header portion that is smaller than the header portion for a conventional PCI packet. The devices may be an endpoint device, such as a graphics processor, and a chipset, such as a root-complex. The reduced size header improves the bus throughput efficiency of the computer system and reduces power requirements for the computer system.
申请公布号 US2007130397(A1) 申请公布日期 2007.06.07
申请号 US20050253870 申请日期 2005.10.19
申请人 NVIDIA CORPORATION 发明人 TSU WILLIAM P.
分类号 G06F13/38 主分类号 G06F13/38
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